Generally a DRAM (Dynamic Random Access Memory) is provided with a plurality of memory cell arrays for storing binary contents, and a decoder for selecting the plurality of memory cell arrays in accordance with address. Each memory cell consists of a capacitor and an MOS transistor. For the MOS transistor in the memory cell, an NMOS transistor that is easy to manufacture and occupies small dimension and does not have burdensome power requirements is frequently used. The NMOS transistor, however, has a shortcoming of losing source voltage as much as its threshold voltage. Further, the memory cell arrays are equipped with word lines to which the NMOS transistors of the plurality of memory cells are commonly contacted. To normal drive the NMOS transistors, those word lines should be supplied with a high-power signal Vpp which is higher than that of the source voltage.
A driving circuit for driving the word line is contacted to the word line of memory cell array and between the decoders, and the driving circuit generates a high-power word line driving signal so as to drive the plurality of memory cells contacted to the word line in accordance with the output of the decoder.
Then, referring to FIG. 1, an architecture and operation of a conventional sub word line driving circuit will be discussed as well as its shortcomings.
The conventional sub word line driving circuit as shown in FIG. 1 consists of a first sub word line driving and clearing circuit part 10 for driving and clearing a first word line, and a second word line driving and clearing circuit part 20 for driving and clearing a second word line.
The first sub word line driving and clearing circuit 10 includes a PMOS transistor P1 for driving word lines, the PMOS transistor P1 applying a word line boosting voltage pxi into a first word line WL01 and activating when a word line driving signal mwl_01 is "low"; a first NMOS transistor N1 for clearing word lines, the NMOS transistor N1 emitting the potential level of the first word line WL01 into a ground voltage Vss and disabling when the word line driving signal mwl_01 is "high"; and a second NMOS transistor N2 for clearing word lines, the second NMOS transistor N2 emitting the potential level of the first word line WL01 into the ground voltage Vss according to a word line boosting bar voltage signal pxib and disabling.
Further, the second word line driving and clearing circuit part 20 includes: a PMOS transistor P2 for driving word lines, the PMOS transistor P2 applying the word line boosting signal pxi into a second word line WL10 and activating when the word line driving signal mwl_01 is "low"; a third NMOS transistor N3 for clearing word lines, the third NMOS transistor N3 emitting the potential level of the second word line WL10 into the ground voltage Vss and disabling when the word line driving signal mwl_10 is "high"; and a fourth NMOS transistor N4 for clearing word lines, the fourth NMOS transistor N4 emitting the potential level of the second word line WL10 into the ground voltage Vss according to the word line boosting bar voltage signal pxib and disabling.
The operation according to the foregoing structure is as follows. The word line driving signal mwl_01 is applied with low potential ("low") below the threshold voltage of the PMOS transistor P1, and then the word line boosting signal pxi is applied through the PMOS transistor P1 to the first word line WL01, thereby activating the first word line WL01.
Meanwhile, the word line driving signal mwl_01 is applied with high potential ("high") beyond the threshold voltage of the NMOS transistor N1 and then the NMOS transistor N1 is turned on, thereby emitting the potential level of the first word line WL01 into the ground voltage Vss. At this time, the NMOS transistor N2 is also turned on when the first word line WL01 is disabled, thereby emitting the potential level of the first word line WL01 into the ground voltage Vss.
Operation of the second word line driving and clearing circuit part 20 is same as that of the first word line driving and clearing circuit part 10.
FIG. 2 is a planar view for showing a layout of a conventional sub word line driving circuit, and FIG. 3 is a layout of an NMOS transistor in the conventional sub word line driving circuit shown in FIG. 1. Herein, the reference "a" is an area being in contact with the first word line, and the reference "b" is an area being in contact with the second word line, the reference "c" is a gate poly 1 area, and the reference "d" is an ISO area.
Referring to the above-described layouts, junctions of the NMOS transistors N1 and N2 are merged at a point and junctions of the NMOS transistors N3 and N4 are merged at a point. And then, gate terminals of the NMOS transistors N2, N4 are merged at the same point since they have the same node.
In order to drive a word line activated as "high" into the disabled "low" state, in the conventional sub word line driving circuit as constituted above, two NMOS transistors N1 and N2 for disabling the word line are turned on and make the word line "low" state. At this time, speed of disabling the word line varies depending on the sizes of the NMOS transistors N1,N2. Therefore, when the NMOS transistors N1 and N2 are increased in their sizes to increase the speed of the word line to be "off" state, the layout dimension of the sub word line is also increased. While the NMOS transistors N1 and N2 are decreased in their sizes to decrease the layout dimension of the NMOS transistors N1 and N2, the speed for disabling the word line is also decreased.
Accordingly, the present invention is provided to solve the foregoing problem and the object of the present invention relates to provide a sub word line driving circuit characterized in that a word line is promptly disabled without increasing layout dimension thereby reducing the set-up hold time.